In accordance with an exemplary scenario, fabricated circuits are tested so as to verify that no input or output of a logic gate within the fabricated circuits gets stuck (or is maintained) at a fixed value (e.g., logic 0 or logic 1) during operation due to unforeseen circumstances, such as, for example, a short circuit. In order to mitigate the above-mentioned issues, the fabricated circuits are subjected to scan tests. The scan tests are performed on integrated circuits, including a combinatorial part and a sequential part. The sequential part may include a sequence of one or more storage elements (e.g. flip-flops). During a scan test, the storage elements constituting the sequential part of the integrated circuits are coupled or connected as a scan chain, and a test vector is transferred into the scan chain through one or more input test pins provided on the integrated circuit. The integrated circuit is placed in an evaluation mode (e.g., a capture phase) so as to cause one or more inputs and states of one or more storage elements to be evaluated, and a corresponding response vector obtained in the evaluation mode is shifted out through one or more output test pins. The bit values in the response vector are compared with an expected output so as to determine fault conditions in the integrated circuit.